1. Field of the Invention
The present invention relates in general to a timing signal generator that uses a direct digital frequency synthesizer to control the period between successive pulses of its output timing signal.
2. Description of Related Art
Timing signal generators produce output pulses at controlled intervals that are useful for initiating events. For example, an integrated circuit (IC) tester transmits test signals to an IC device under test (DUT) and samples DUT output signals to determine whether the DUT is behaving as expected. A tester uses timing signals to initiate state changes in the test signals and to trigger the sampling of DUT output signals. To be able to test increasingly higher frequency digital integrated circuits, testers need increasing higher frequency timing signal generators that can control the timing of signal pulse edges with increasingly higher accuracy and resolution.
FIG. 1 illustrates a simple prior art timing signal generator employing a divide-by-N counter 10 and a pattern generator 12. Counter 10 produces a TIMING signal pulse in response to every N pulses of a periodic clock signal (ROSC) produced by a stable reference oscillator. A programmable pattern generator 12 clocked by the TIMING signal generators a sequence of data values that controls the count limit N of counter 10. In response to a pulse of an input START signal counter 10 counts the number N of ROSC signal pulses indicated by the data output of pattern generator 12 and then produces a first pulse of the TIMING signal. That timing pulse tells pattern generator 12 to supply a next value of N to counter 10. Thus the value of N pattern generator 12 produces in response to each TIMING signal pulse controls the time interval between that timing signal pulse and the next. Accordingly pattern generator 12 must be capable of producing a separate N data value for each successive pulse of the TIMING signal.
Note that the timing resolution of the timing signal generator of FIG. 1 is equal to the period PR of the ROSC signal since all TIMING signal pulses will have the same phase relative to the ROSC signal.
FIG. 2 illustrates a higher resolution timing signal generator which also employs a divide-by-N counter 14 controlled by a pattern generator 16. However the output T0 of counter 14 is applied to a tapped delay line 18 formed by a series of Mxe2x88x921 logic gates 20, each delaying the T0 signal by PROSC/M to produce a set of tap signals T1-T(Mxe2x88x921). Signals T0-T(Mxe2x88x921) drive inputs of a multiplexer 20 which responds to an input value K by selecting the Kth tap signal to drive the TIMING signal. Pattern generator 16, clocked by the T0 signal, updates the values of N and K on each TIMING signal pulse. Thus the timing signal generator of FIG. 2 can place TIMING signal edges with a resolution of 1/Mth of the period of the ROSC signal.
One difficulty with the use of tapped delay line 18 is that it is difficult to accurately control the delays of gates so that each gate has a delay of 1/Mth of the period of the ROSC signal since gate delays are subject to temperature and process variations. Thus while the timing signal generator of FIG. 2 may have high resolution, the difficulty in controlling the delays of gates 20 can render it somewhat inaccurate.
FIG. 3 illustrates a more inherently accurate timing signal generator that also includes a divide-by-N counter 22, a pattern generator 24, a tapped delay line 26 and a multiplexer 28. In this circuit, pattern generator 24 supplies the value of K to multiplexer 28 but does not supply the value of N to divide-by-N counter 22; the value of N is fixed and does not change on the fly after the timing signal generator starts generating the TIMING signal in response to a START signal pulse. Thus the T0 signal has a fixed period that is 1/Nth that of the ROSC signal. Tapped delay line 26 has M gates 32 so that the last (Mth) tap signal TM will be in phase with the T0 output of divide-by-N counter 22 when the average delay of each of the M gates 32 is 1/Mth that of the T0 signal. The delay of each gate 32 is a function of its switching speed, and the gate""s switching speed is in turn a function the voltage of an input control signal CONT. A phase lock controller 30 compares the phases of the T0 and TM signals and adjusts the delay of gates 32 by adjusting the CONT signal voltage to keep the TM signal in phase with the T0 signal. This ensures that the average delay provided by gates 32 is 1/Mth the period of the T0 signal. This phase locking system keeps the delay of gates 32 stable regardless of temperature changes in the IC implementing delay line 18. Thus the timing signal generator of FIG. 3 is inherently more accurate than the timing signal generator of FIG. 2. However since the delay of each gate 20 of FIG. 2 is 1/Mth of the ROSC signal period while the delay of each gate 32 of FIG. 3 is N/Mth of the ROSC signal period, the resolution of the signal generator of FIG. 3 is lower than the resolution of the signal generator of FIG. 2 unless the value of N is set to one.
Since phase lock controller 30 uses feedback to control the delay of gates 32, the inherent delay of its feedback loop can cause some jitter (variation) in the timing of edges. Timing signal inaccuracies also arise because process and temperature variations from gate-to-gate on the same IC will cause logic gates 32 to have slightly differing delays.
The timing signal generator of FIG. 3 also xe2x80x9ccyclizesxe2x80x9d the TIMING signal in the sense that the TIMING signal is restricted to having no more than one pulse every N cycles of the ROSC signal, where N is a fixed value. During any of the N cycle periods of the ROSC signal in which the TIMING signal is not to convey a pulse, pattern generator 24 must tell multiplexer 28 not to drive the TIMING signal with any of its input tap signals. Thus while pattern generator 16 of FIG. 2 must include one N,K pair for each pulse of the TIMING signal to be produced, pattern generator 24 must include one K data value for every N cycles of the ROSC signal, regardless of the number of TIMING signal pulses to be produced. Hence when we try to increase resolution with which pulses of the TIMING signal are timed by reducing the value of N, we increase the length of the data sequence pattern generator 24 must produce. Thus the value of N supplied to counter 22 represents a trade-off between timing resolution and the sequence generating capacity of pattern generator 24.
What is needed is an accurate, high resolution, high frequency timing signal generator that makes efficient use of pattern generation resources and which does not rely on logic gate delay controlled by phase lock feedback as references for controlling intervals between output signal pulses.
A timing signal generator in accordance with the invention includes a direct digital frequency synthesizer (DDFS), a divide-by-N counter, and a pattern generator to produce a TIMING signal conveying a timed sequence of pulses.
The pattern generator produces data pair (FREQ,N) in response to each pulse of the TIMING signal and that data pair indicates a time interval that is to occur before a next TIMING signal pulse.
The DDFS, using a stable high frequency reference clock signal (ROSC) as a timing reference, generates an analog output sine wave signal (SINE) having a frequency controlled by the current FREQ data output of the pattern generator.
The divide-by-N counter produces the timing signal pulses. It counts cycles of the SINE signal occurring since it last produce a TIMING signal pulse and generates a next TIMING signal when it has counted the number of SINE signal pulses indicated by the current N data output of the pattern generator.
Thus successive (FREQ, N) pairs produced by the pattern generator control the duration of the interval preceding each successive pulse of the TIMING signal. The FREQ data controls the frequency (and therefore the period) of the SINE signal produced by the DDFS, while the N data controls the number of SINE signal periods the counter is to wait before generating the next TIMING signal pulse.
Unlike typical prior art timing signal generators, a timing signal generator in accordance with the invention does not rely on logic gate delays controlled by phase lock feedback as references for controlling intervals between TIMING signal pulses. Thus the TIMING signal is not subject to pulse timing inaccuracies arising from jitter due to temperature and process variations affecting gate delays or due to oscillations in a feedback control circuit controlling gate delays. When the DDFS is implemented using high speed semiconductor technology capable of responding, for example, to a 100 GHz ROSC signal to produce an output SINE signal in the range of 2.5 to 5 GHz, the timing signal generator in accordance with the invention can provide sub-picosecond timing resolution with very little jitter. Also since the spectral content of the TIMING signal is entirely predictable, the dominant form of jitter is periodic rather than random. Thus, for example, when the timing signal generator is employed to clock a digitizer, the digitizer""s output data can be processed to correct for the predictable jitter in the TIMING signal.
The claims portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.